HAL DCACHE initialization and configuration functions migration

The goal of this page is to show how to migrate the initialization sequence using STM32CubeMX2:

  • Open STM32CubeMX2 DCACHE configuration panel.

  • Configure the SW layer HAL

  • Configure the additional DCACHE features if needed.

  • Configure the NVIC if the application requires the DCACHE to be used in IT mode.

  • Generate the code

HAL DCACHE configuration panel

Create a new project with the STM32CubeMX2, then start the initialization and the main configuration.

Project configuration panel

HAL DCACHE additional features configuration

Configure the additional DCACHE features if needed.

DCACHE additional feature configuration

NVIC configuration

Configure the NVIC in case of an interrupt.

DCACHE NVIC configuration

Generated DCACHE initialization and de-initialization sequences

The DCACHE initialization and de-initialization sequences are generated in the mx_dcache1_hal_init function in mx_dcache.c file under $YOUR_PROJECT_NAME$/$YOUR_PROJECT_NAME$_SW/generated/STM32Cube_CodeGen.

Related concepts:

STM32CubeMX2 Generated with user values

Topic

HAL1 code snippet

HAL2 code snippet

DCACHE init and config sequences 

static void MX_DCACHE1_Init(void)
{
  hdcache1.Instance = DCACHE1;
  hdcache1.Init.ReadBurstType = DCACHE_READ_BURST_WRAP;
  if (HAL_DCACHE_Init(&hdcache1) != HAL_OK)
  {
    Error_Handler();
  }




  HAL_DCACHE_Monitor_Start(&hdcache1, DCACHE_MONITOR_READ_HIT)
}

void HAL_MspInit(void)
{
  ...

  /* DCACHE1_IRQn interrupt configuration */
  HAL_NVIC_SetPriority(DCACHE1_IRQn, 0, 0);
  HAL_NVIC_EnableIRQ(DCACHE1_IRQn);
}

hal_dcache_handle_t *mx_dcache1_init(void)
{
  HAL_RCC_DCACHE1_EnableClock();

  if (HAL_DCACHE_Init(&hDCACHE1, HAL_DCACHE1) != HAL_OK)
  {
    return NULL;
  }

  if (HAL_DCACHE_SetReadBurstType(&hDCACHE1, HAL_DCACHE_READ_BURST_WRAP) != HAL_OK)
  {
    return NULL;
  }

  HAL_DCACHE_EnableMonitors(&hDCACHE1, HAL_DCACHE_MONITOR_READ_HIT);




  /* Enable the interruption for DCACHE */
  HAL_CORTEX_NVIC_SetPriority(DCACHE1_IRQn, HAL_CORTEX_NVIC_PREEMP_PRIORITY_0, HAL_CORTEX_NVIC_SUB_PRIORITY_0);
  HAL_CORTEX_NVIC_EnableIRQ(DCACHE1_IRQn);

  return &hDCACHE1;
}

DCACHE deinit sequences 

static void Dcache_deinit(void)
{
 if (HAL_DCACHE_DeInit(&hdcache1) != HAL_OK)
 {
   Error_Handler();
 }
}

void HAL_DCACHE_MspDeInit(DCACHE_HandleTypeDef* hdcache)
{
  if(hdcache->Instance==DCACHE1)
  {
    /* Peripheral clock disable */
    __HAL_RCC_DCACHE1_CLK_DISABLE();

    /* DCACHE1 interrupt DeInit */
    HAL_NVIC_DisableIRQ(DCACHE1_IRQn);
  }
}

void mx_dcache1_deinit(void)
{
  /* Disable the interruption for DCACHE */
  HAL_CORTEX_NVIC_DisableIRQ(DCACHE1_IRQn);

  (void)HAL_DCACHE_DeInit(&hDCACHE1);

  HAL_RCC_DCACHE1_Reset();
  HAL_RCC_DCACHE1_DisableClock();
}

DCACHE IRQ handler sequences 

void DCACHE_IRQHandler(void)
{
  HAL_DCACHE_IRQHandler(hdcache1);
}

void DCACHE1_IRQHandler(void)
{
  HAL_DCACHE_IRQHandler(&hDCACHE1);
}